Embodiments of the present invention relates generally to semiconductor devices and, more specifically, to damascene gates having protected shorting regions and related methods for their manufacture.
Current integrated circuit (IC) designs often employ contact sizes, gate sizes, and operating voltages that risk unintentional contact etching and/or contact-to-gate electrical shorts. Gate corners are particularly susceptible to such contact-to-gate shorts. One solution to this problem is increasing the space between contacts and gate corners. Such solutions are unsatisfactory, however, due to the increase in gate size necessitated by such increased space and the attendant impairment of device performance.